RISC-V: They Should Have Known Better

	RISC-V: They Should Have Known Better(dmitry.gr)
	379 points by dmitrygr 7 days ago \| 434 comments
	tl;dr: The author argues RISC-V's ISA is poorly designed: near-universal optionality (even CSRs, multiplication, and interrupt handling extensions) fragments the ecosystem, immediate encodings are needlessly scrambled, and compressed instructions have conflicting meanings across extensions that can silently corrupt behavior. Obvious features like register+register addressing, bit-test-and-branch, and bitfield ops are missing, forcing kludges like the RVA23 "profile" to retroactively mandate basics—yet most shipping RISC-V boards don't comply. The author expects RISC-V to win low-end microcontroller and accelerator-babysitter roles on price alone, but not serious desktop/server compute.
	HN Discussion: ~RISC-V is good enough as a hobby/embedded ISA and its flaws can be worked around ↓RISC-V is better understood as an ISA generation framework, so fragmentation is inevitable regardless of design ↓RISC-V's openness and lack of IP encumbrance matters more than technical shortcomings ↓Major industry adoption (AMD, NVIDIA, Meta) validates RISC-V as sufficient despite flaws ↑Firsthand experience confirms the article's criticisms about fragmentation and poor interrupt/extension design